Integrated circuits utilize interconnects to transmit signals from one portion of the circuit to another portion of the circuit. Interconnects within an integrated circuit typically comprise wires formed in a metal layer of the integrated circuit. Each wire is associated with a resistance and a capacitance that is related to the physical design of the wire (e.g., cross section, length, etc.). Transmitting signals on these wires is not instantaneous. Changing a signal on the wire requires the wire to be charged or discharged. There is a time delay for a signal to travel down a wire that is characterized by an RC factor associated with the wire (i.e., a resistance of the wire in ohms multiplied by a capacitance of the wire). Because both resistance of a wire and capacitance of a wire increase linearly with a wire's length, the time delay increases as a square of the wires length.
In order to decrease the time delay associated with a long interconnect, active circuit(s) can be introduced along the long interconnect to break the long interconnect up into multiple shorter interconnects. Because the time delay of the short interconnects, added together, is less than the time delay of the long interconnect, a relatively faster link can be provided over the same linear distance of the integrated circuit. FIG. 1 illustrates a conventional CMOS (Complementary Metal Oxide Semiconductor) repeater link 100, in accordance with the prior art. The link 100 includes a plurality of interconnects (e.g., 112, 114, 116, 118, etc.) connected to a number of repeaters (e.g., 102, 104, 106, etc.). The repeaters shown in FIG. 1 are conventional CMOS inverters. It will be appreciated that an even number of repeaters (and an odd number of interconnects) may be used to ensure the signal at the end of the link 100 is the same as the signal at the beginning of the link 100.
The link 100 may be used to transmit a signal, A, from one end of the link 100 to the other end of the link 100. For example, the interconnect 112 may be charged to high potential (Vdd) to match a logic high state of signal A. The inverter 102 then discharges interconnect 114 to a low potential (Vss) to match an inverted state of signal A, i.e., a logic low state of signal Ā. The inverter 104 then charges interconnect 116 to a high potential (Vdd) to match an inverted state of signal Ā, i.e., a logic high state of signal A. The inverter 106 then discharges interconnect 118 to a low potential (Vss) to match an inverted state of signal A, i.e., a logic low state of signal Ā, and so forth until the end of the link is reached and the last interconnect is charged to a high potential (Vdd) to match a logic high state of signal A at the beginning of the link 100.
A common way to define the power dissipation of conventional CMOS repeater links, such as the link 100 of FIG. 1, is shown in Equation 1.P=A*F*C*V2  (Eq. 1)
In Equation 1, the term A refers to an activity factor of the data, the term F refers to a frequency of the data clock, the term C refers to a capacitance of the wire, and the term V refers to a voltage swing of the signal, which is typically between a low supply voltage, Vss (i.e., a ground potential), and a high supply voltage, Vdd. The activity factor of the data refers to a relative measurement of the number of transitions between logic low and logic high of the signal relative to a number of transitions of the data clock. For example, a signal representing a clock, where the signal has alternating positive or negative transitions during each period of the data clock (e.g., 1010101010101010 . . . ) would have an activity factor of 1. The activity factor may be lower where there are very few transitions in the signal (e.g., 00000000111111110000000011 . . . ).
It will be appreciated that the power dissipation depends on the square of the voltage swing on the interconnects of the link 100. One technique for reducing the power dissipation in the links is to reduce the magnitude of the voltage swing in the voltage domain utilized by the link. For example, reducing the voltage swing from 5V to 3V would reduce the power dissipation by more than 60%. Another technique that has been proposed is to split the voltage domain into two voltage domains and stack the links such that each link utilizes a voltage domain associated with a voltage swing of half the magnitude compared to a voltage swing associated with the full-scale voltage domain, a technique known as charge-recycling.
FIG. 2 illustrates a pair of stacked CMOS repeater links 200, in accordance with the prior art. The pair of stacked CMOS repeater links 200 includes a first link in a first voltage domain and a second link in a second voltage domain. As shown in FIG. 2, the first link includes a plurality of interconnects (e.g., 211, 213, 215, 217, etc.) connected to a number of repeaters (e.g., 201, 203, 205, etc.). The first link operates in a first voltage domain having a high supply voltage of Vdd and a low supply voltage of
            V      dd        2    ,which is provided by a voltage regulator 220, such as the op amp coupled to a pair of equally sized resistors (each labeled R) placed in series between the high supply voltage and the low supply voltage. The voltage regulator is required to keep the mid-range supply voltage
      V    dd    2stable. Without the voltage regulator, the mid-range supply voltage could drift due to the uneven charging and discharging of the interconnects in the pair of stacked CMOS repeater links 200 based on the uneven transitions between the pair of signals transmitted over the pair of links. The second link includes a plurality of interconnects (e.g., 212, 214, 216, 218, etc.) connected to a number of repeaters (e.g., 202, 204, 206, etc.). The second link operates in a second voltage domain have a high supply voltage of
      V    dd    2and a low supply voltage of Vss (e.g., a ground potential). Again, the repeaters shown in FIG. 2 are conventional CMOS inverters. It will be appreciated that an even number of repeaters (and an odd number of interconnects) may be used to ensure the signals at the end of the pair of stacked CMOS repeater links 200 are the same as the signals at the beginning of the pair of stacked CMOS repeater links 200.
The stacked CMOS repeater links 200 can be used to transmit a pair of signals (A/B) in a similar manner of the link 100, described above. The signal A may be transmitted in the first voltage domain, and the signal B may be transmitted in the second voltage domain. Because signals A and B are independent signals, the state of signal A and the state of signal B will transition differently such that both A and B can be both logic high, both logic low, or one logic high and one logic low at any given time t. Given that the transitions for signals A/B are different, the inverters (e.g., 201, 202, 203, 204, 205, 206, etc.) will charge or discharge the interconnects (e.g., 211, 212, 213, 214, 215, 216, 217, 218, etc.) in an uneven manner based on the states of the signals, which could cause the mid-range supply voltage to drift without the inclusion of the voltage regulator 220.
Stacking the links in the manner shown in FIG. 2 will reduce power dissipation of the link due to the reduction in the voltage swing applied to each interconnect. However, much of this reduction in power dissipation may be given back in terms of the power required to hold the mid-range supply voltage steady using the voltage regulator 220, both in terms of the power dissipated through the resistors and losses in the op amp as well as losses associated with routing the mid-range supply voltage to each of the repeaters in the links. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.